--------------------------------------------------------------------------------
Running performance on file test\p30_deffer_impl_flat.ps
-------------------- NV40 --------------------
Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v65.04
IPU0 ------ Simplified schedule: --------

Pass |  Unit  |  uOp |  PC:  Op
-----+--------+------+-------------------------
   1 |   SCT0 |  div |   0:  TEXh h1, f[TEX1], TEX0;
     |   SCT1 |  mov |   1:  NRMh h4.xyz, f[TEX3];
     |    TEX |  tex |   0:  TEXh h1, f[TEX1], TEX0;
     |    SRB |  nrm |   1:  NRMh h4.xyz, f[TEX3];
     |   SCB1 |  mul |   2:  MOVh h0.w, const;
     |        |      |
   2 |   SCT1 |  mul |   4:  MOVh h4.w, h1;
     | SCB0/1 |  mad |   5:  MADh h6, h1.xyzx, const.xxxy, const.yyyz;
     |        |      |
   3 |   SCT0 |  div |   7:  MADh h0.xyz, h4, const.xxx-, f[TEX2];
     |   SCB0 |  mad |   7:  MADh h0.xyz, h4, const.xxx-, f[TEX2];

Pass   SCT  TEX  SCB
   1:  50% 100%  25%
   2:  25%   0% 100%
   3:  75%   0%  75%
   4:   0%   0%   0%

MEAN:  37%  25%  50%

Pass   SCT0  SCT1   TEX  SCB0  SCB1
   1:  100%    0%  100%    0%  100%
   2:    0%  100%    0%  100%  100%
   3:  100%    0%    0%  100%    0%
   4:    0%    0%    0%    0%    0%

MEAN:   50%   25%   25%   50%   50%
Cycles: 4.00 :: R Regs Used: 3 :: R Regs Max Index (0 based): 3
Max register used is > number of registers used, registers are not being used efficiently
--------------------------------------------------------------------------------
Running performance on file test\p30_deffer_impl_flat.ps
-------------------- NV40 --------------------
Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v81.95
Cycles: 2.00 :: R Regs Used: 3 :: R Regs Max Index (0 based): 3
Max register used is > number of registers used, registers are not being used efficiently
Pixel throughput (assuming 1 cycle texture lookup) 3.20 GP/s
--------------------------------------------------------------------------------
Running performance on file test\p30_deffer_impl_flat.ps
-------------------- G70 --------------------
Target: GeForce 7800 GT (G70) :: Unified Compiler: v81.95
Cycles: 2.00 :: R Regs Used: 3 :: R Regs Max Index (0 based): 3
Max register used is > number of registers used, registers are not being used efficiently
Pixel throughput (assuming 1 cycle texture lookup) 4.80 GP/s
